Semiconductor device and method of fabricating the same

ABSTRACT

There is provided a high quality liquid crystal panel having a thickness with high accuracy, which is designed, without using a particulate spacer, within a free range in accordance with characteristics of a used liquid crystal and a driving method, and is also provided a method of fabricating the same. The shape of a spacer for keeping a substrate interval constant is made such that it is a columnar shape, a radius R of curvature is 2 μm or less, a height H is 0.5 μm to 10 μm, a diameter is 20 μm or less, and an angle α is 65° to 115°. By doing so, it is possible to prevent the lowering of an opening rate and the lowering of light leakage due to orientation disturbance.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device including acircuit constructed by thin film transistors (hereinafter referred to asTFTs) and a method of fabricating the same. For example, the presentinvention relates to an electro-optical device typified by a liquidcrystal display panel, and an electronic equipment including such anelectro-optical device as a part.

Incidentally, in the present specification, the term “semiconductordevice” indicates any devices capable of functioning by usingsemiconductor characteristics, and any of the electro-optical device,semiconductor circuit, and electronic equipment is a semiconductordevice.

2. Description of the Related Art

In recent years, attention has been paid to a technique for constructinga thin film transistor (TFT) using a semiconductor thin film (itsthickness is about several to several hundred nm) formed on a substratehaving an insulating surface. The thin film transistor is widely appliedto an electronic device, such as an IC or an electro-optical device, andespecially as a switching element of an image display device, itsdevelopment has been hastened.

As a typical example of the electro-optical device, a liquid crystaldisplay device, an EL display device, or a contact type image sensor canbe cited.

In general, the liquid crystal display device includes a pair ofsubstrates which are opposed to each other at a certain substrateinterval, particulate spacers for keeping the certain substrateinterval, and a liquid crystal material sealed between the substrates.

The substrate interval of the liquid crystal display device is normallyset to 1 to 20 μm, and this must be uniformly controlled with accuracyof about ±0.1 μm. This is because if fluctuation occurs in the substrateinterval, not only deterioration in display quality, such as generationof irregular color or interference fringe, is caused, but also trouble,such as circuit damage or disabled display, is caused by contact ofelectrodes when the substrate interval is narrowed by an external force.Like this, the spacer is an important member for maintaining theperformance of the liquid crystal display element.

Hereinafter, a conventional method of fabricating a liquid crystaldisplay device (TFT-LCD) will be described in brief.

First, a pair of substrates are prepared. TFT elements and pixelelectrodes are formed in matrix form on one of the substrates.Electrodes, color filters or the like are formed on the other substrate.Next, after an alignment film is formed on each of the pair ofsubstrates, a rubbing processing is performed.

Next, particulate spacers are uniformly sprayed on the alignment film ofeither one of the substrates. Next, the one substrate is combined withthe other substrate, and their peripheral portions are sealed with anadhesive for sealing, so that a liquid crystal cell is formed. Next,after the liquid crystal cell is filled with a liquid crystal materialby a vacuum injection method, an injection port is sealed.

The foregoing flow of steps is a general fabricating process of aTFT-LCD.

In the above conventional steps, it is difficult to uniformly spray theparticulate spacers, and there have been problems that transmissivity islowered by aggregation of the spacers, and an element just under thespacer is destroyed to generate a leak or short circuit.

Besides, in the step of injecting the liquid crystal material by thevacuum injection method, center portions of the substrates becomerecess-shaped at both surfaces by pressurization at the time ofinjection, and in this periphery, the conventional particulate spacerdoes not have sufficient compression strength and is destroyed, or thespacer is moved and the trace of the movement causes orientationdefects.

In the case where the generally used conventional particulate spacers(glass beads, plastic beads, etc.) are used, there is adopted a methodof spraying the particulate spacers onto one of substrates. Thus, thespacers are disposed on a pixel electrode, and block incident light ordisturb the orientation of liquid crystal molecules. As a result, it hasbeen difficult to adjust the transmitted light amount or coloring.Besides, the particulate spacers are easily charged with staticelectricity, so that the spacers become easily aggregate and aredifficult to be uniformly distributed.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a high quality liquidcrystal panel having a thickness with high accuracy, which is designed,without using particulate spacers, within a free range in accordancewith characteristics of a used liquid crystal and a driving method, andis also to provide a method of fabricating the same.

According to an aspect of the present invention, a semiconductor deviceincludes a first substrate, a second substrate, and a plurality ofcolumnar spacers disposed between the first substrate and the secondsubstrate and maintaining an interval between the first substrate andthe second substrate.

Besides, according to another aspect of the present invention, asemiconductor device includes a first substrate, a second substrate, anda plurality of columnar spacers disposed between the first substrate andthe second substrate, wherein a radius R of curvature of each of thecolumnar spacers is 2 μm or less, preferably 1 μm or less.

Besides, in the foregoing respective structures, a height H of each ofthe columnar spacers is 0.5 μm to 10 μm, preferably 1.2 μm to 5 μm.

Besides, in the foregoing respective structures, a width L1 of each ofthe columnar spacers is 20 μm or less, preferably 7 μm or less.

Besides, in the foregoing respective structures, an angle α between atangent plane at a center of a side of each of the columnar spacers anda substrate surface is 65° to 115°.

Besides, in the foregoing respective structures, each of the columnarspacers includes a flat surface at its top portion.

Besides, in the foregoing respective structures, a sectional shape ofeach of the columnar spacers in a radial direction is a circle, anellipse, a triangle, a quadrilateral, or a polygon having sides morethan the former.

Besides, in the foregoing respective structures, each of the columnarspacers is made of an insulating material.

Besides, in the foregoing respective structures, each of the columnarspacers is formed over a contact portion where a TFT and a pixelelectrode are connected to each other.

Besides, the columnar spacers may be formed only at a sealing region, ormay be formed at a sealing region and a region of a driver circuit wherean element does not exist. Besides, the columnar spacers may be formedat the sealing region and a pixel portion, or may be formed at a regionof the driver circuit where an element does not exist and the pixelportion. Besides, the columnar spacers may be formed at the sealingregion and a region between the driver circuit and the pixel portion, orthe columnar spacers may be formed at a region between the drivercircuit and the pixel portion, and the pixel portion.

Besides, the columnar spacers may be formed at a sealing region, over aregion of a driver circuit where an element does not exist, and at apixel portion, or the columnar spacers may be formed over a region ofthe driver circuit where an element does not exist and at a regionbetween the driver circuit and the pixel portion. Besides, the columnarspacers may be formed at the sealing region, over a region of the drivercircuit where an element does not exist, at a region between the drivercircuit and the pixel portion, and the pixel portion, or the columnarspacers may be formed at a region between the sealing region and thepixel portion. Besides, the columnar spacers may be formed at a regionbetween the sealing region and the driver circuit, or the columnarspacers may be formed at a region between the sealing region and an endportion of the substrate. Besides, the columnar spacers may be formed atall regions of the substrate.

Besides, in the foregoing respective structures, in the case where thecolumnar spacers are formed to be in contact with an alignment film, apretilt angle of the alignment film is 4° to 5°.

Besides, in the foregoing respective structures, in the case where thecolumnar spacers are covered with an alignment film, a pretilt angle ofthe alignment film is 6° to 10°.

Besides, according to another aspect of the present invention, asemiconductor device includes a display device equipped with a firstsubstrate, a second substrate, and a plurality of columnar spacersdisposed between the first substrate and the second substrate, and atouch panel equipped with an optical detecting element.

Besides, according to another aspect of the present invention, asemiconductor device includes a display device equipped with a firstsubstrate, a second substrate, and a plurality of columnar spacersdisposed between the first substrate and the second substrate, and atouch panel equipped with a pressure sensitive type detecting element.

Besides, according to another aspect of the present invention, asemiconductor device includes a display device equipped with a firstsubstrate, a second substrate, and a plurality of columnar spacersdisposed between the first substrate and the second substrate, and atouch panel equipped with a capacitive type detecting element.

Besides, according to another aspect of the present invention, a methodof fabricating a semiconductor device comprises a first step of forminga TFT on a substrate, a second step of forming a flattening film tocover the TFT, a third step of forming an opening in the flattening filmto reach to the TFT and forming a pixel electrode, a fourth step s offorming an alignment film on the pixel electrode, a fifth step ofperforming a rubbing processing on the alignment film, and a sixth stepof forming a columnar spacer made of an insulating film over a contactportion where the TFT is connected to the pixel electrode.

Besides, according to another aspect of the present invention, a methodof fabricating a semiconductor device comprises a first step of forminga TFT on a substrate, a second step of forming a flattening film tocover the TFT, a third step of forming an opening in the flattening filmto reach to the TFT and forming a pixel electrode, a fourth step offorming a columnar spacer made of an insulating film over a contactportion where the TFT is connected to the pixel electrode, a fifth stepof forming an alignment film to cover the pixel electrode and thecolumnar spacer, and a sixth step of performing a rubbing processing onthe alignment film.

In the foregoing structure, the step of forming the columnar spacer madeof the insulating film includes a step of forming the insulating filmand a step of patterning the insulating film so that the columnar spaceris formed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are a SEM observation photograph of a columnar spacer ofthe present invention and its schematic view.

FIGS. 2A to 2C are views showing examples of arrangement of columnarspacers and SEM observation photographs.

FIGS. 3A to 3E are views showing fabricating steps of the presentinvention.

FIG. 4 is a view showing a flowchart of fabricating steps of the presentinvention.

FIGS. 5A to 5F are views showing fabricating steps of an AM-LCD.

FIGS. 6A to 6F are views showing fabricating steps of the AM-LCD.

FIGS. 7A to 7D are views showing fabricating steps of the AM-LCD.

FIGS. 8A and 8B are views showing fabricating steps of the AM-LCD.

FIG. 9 is a sectional structural view of a TFT.

FIG. 10 is a view showing an outer appearance of an AM-LCD.

FIG. 11 is a view showing a structure of a pixel portion and a drivercircuit.

FIG. 12 is a top view showing a pixel structure.

FIGS. 13A and 13B are views showing examples of a connection portion toan external terminal.

FIGS. 14A to 14E are views showing fabricating steps of the presentinvention.

FIG. 15 is a view showing a flowchart of fabricating steps of thepresent invention.

FIGS. 16A and 16B are views showing fabricating steps of an AM-LCD.

FIGS. 17A and 17B are SEM observation photographs of columnar spacers ofthe present invention.

FIGS. 18A and 18B are views showing examples of arrangement of columnarspacers.

FIGS. 19A to 19C are views showing examples of arrangement of columnarspacers.

FIG. 20 is a sectional structural view of an active matrix type liquidcrystal display device.

FIG. 21 is a sectional structural view of an active matrix type liquidcrystal display device.

FIGS. 22A and 22B are views showing display devices each including atouch panel.

FIG. 23 is a view showing a structure of an active matrix type ELdisplay device.

FIG. 24 is a view showing characteristics of light transmissivity of athresholdless antiferroelectric mixed liquid crystal to applied voltage.

FIGS. 25A to 25F are views showing examples of electronic devices.

FIGS. 26A to 26D are views showing examples of electronic devices.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A mode of carrying out the present invention will be described belowwith reference to FIGS. 1 to 4.

In the present invention, a columnar spacer is used to keep an intervalbetween a first substrate and a second substrate constant. It isdesirable that the shape of the columnar spacer of the present inventionsatisfies conditions described below.

As shown in FIG. 1B, in the columnar spacer, it is assumed that thewidth (diameter) of a center portion is L1, the width (diameter) of anupper end is L3, and the width (diameter) of a lower end is L2. In stepsshown in FIGS. 3A to 3E (in the case where a columnar spacer 303 isformed on an alignment film 301), values of widths of the columnarspacer itself are made the widths L1 to L3. However, in steps shown inFIGS. 14A to 14E (in the case where an alignment film 1103 is formed ona columnar spacer 1102), values obtained by adding the thickness of thealignment film to the columnar spacer itself are made the widths L1 toL3. Incidentally, the width L2 is a width of a region where there existsa columnar spacer material having a thickness of 0.2 μm or more from aplane prior to formation of the columnar spacer. It is necessary thatthe width L1 of the center of the columnar spacer functionssatisfactorily as a spacer, and it is desirable that the width is 20 μmor less, preferably 10 μm or less, more preferably 7 μm or less.

Incidentally, in the present specification, the lower end indicates anend portion of a columnar spacer at a first substrate side. The upperend indicates a top portion of the columnar spacer. The top portion ofthe columnar spacer of the present invention has a flat surface so thatwhen an external force is applied, a uniform pressure is applied to thecolumnar spacer. Since a spacer made of resin has excellent elasticity,it can suitably absorb the pressure. Besides, differently from aparticulate spacer, the columnar spacer of the present invention comesin contact with an element through a surface, so that the pressure isdispersed, and there does not occur a case where an excessive pressureis applied to one point. The present invention is devised such that theradius R of curvature of an end portion at the top portion of thecolumnar spacer is made 2 μm or less, preferably 1 μm or less, so that auniform pressure is applied to the columnar spacer.

In the present invention, it is preferable that the widths of therespective portions of the columnar spacer are the same, that is,L1=L2=L3. Besides, it is preferable that an angle α between the side ofthe columnar spacer at the center and the substrate surface is made avalue within the range of 65° to 115°.

However, in the case where the columnar spacer is actually formed, theupper end of the columnar spacer becomes an end portion having theradius of curvature of 2 μm or less, preferably 1 μm or less, and ataper portion is formed at the lower end of the columnar spacer, so thatthe relation between the widths becomes L2>L1>L3. At the taper portion,defective orientation in a liquid crystal is apt to occur, and lightleakage occurs around this. In the present invention, the widths are setin the range of 0.8≦L2/L1≦3, so that the light leakage is reduced.Incidentally, in the steps shown in FIGS. 3A to 3E (in the case wherethe columnar spacer is formed on the alignment film), it is desirable toestablish the relation of 1≦L2/L1≦1.1. Besides, in the steps shown inFIGS. 14A to 14E (in the case where the alignment film is formed on thecolumnar spacer), it is desirable to establish the relation of1≦L2/L1≦2.5.

Since a contact area to a second substrate is reduced, when an outerpressure is applied, a large pressure is locally applied. This causesdeterioration of spacer strength. In the present invention, the relationof 0.6≦L3/L1≦1.2 is established, so that the spacer strength isstrengthened.

Since the height H of the columnar spacer can be controlled within afree range through the conditions of forming steps of the columnarspacer, it may be suitably set to a desired value. For example, in aliquid crystal display device, according to a liquid crystal material(TN liquid crystal, ferroelectric liquid crystal, antiferroelectricliquid crystal, etc.) used for the device, the height is set to anoptimum substrate interval (0.5 μm to 10 μm, preferably 1.2 μm to 5 μm).

As a material of the columnar spacer, an insulating material (insulatingfilm) made of a resin material is desirable. An insulating film made ofa resin material such as polyimide can be formed by applying a solution,and an insulating film made by solution application is very suitable forfilling minute holes. Of course, a silicon oxide film or the like formedby applying a solution may be used. In the case where an insulating filmmade of a resin material is used, a photopolymerization type insulatingfilm may be used, or a thermal polymerization type insulating film maybe used. Especially when a positive or negative photosensitive resin isused, the columnar spacer can be formed through a simple step, so thatit is preferable. Besides, in order to avoid photodeterioration, it isdesirable to use a resin material having negative photosensitivity.

A sectional shape of the columnar spacer in the radial direction may bea circle or an ellipse. Besides, the shape may be a triangle, aquadrilateral, or a polygon having sides more than the former.

As shown in FIG. 2A, the columnar spacers are disposed regularly. InFIG. 2A, although such a structure is adopted that one columnar spacer202 is disposed for every 6 pixels (6 rows×1 column), the invention isnot particularly limited, and the columnar spacers have only to bedisposed at a density of 10 to 200 ones per mm². In FIG. 2A, referencenumeral 201 designates a pixel electrode; and 203, a contact portionwhere a columnar spacer is not formed. In FIG. 2A, although the columnarspacer is formed at a position over the contact portion where the TFTand the pixel electrode are connected to each other, the position of thecolumnar spacer is not particularly limited. For example, if it isformed over a wiring (source wiring, gate wiring, capacitance wiring,etc.) or over a light-shielding film, it does not influencetransmissivity, so that such a position is preferable. Besides, thecolumnar spacer may be formed at a region other than the pixel portion,for example, a region of a driver circuit where an element does notexist, a sealing region, a region between the pixel portion and thedriver circuit, a region between the pixel portion and the sealingregion, a region between the driver circuit and the sealing region, or aregion between the sealing region and an end portion of a substrate.Incidentally, when the columnar spacer is formed at the region betweenthe sealing region and the end portion of the substrate, since pressureis uniformly applied in a bonding step and a substrate cutting step, theyield is improved. If a columnar spacer is formed over a wiringextending from an end portion for connection with an FPC to the drivercircuit, the mechanical strength of a portion connecting with the FPCcan be reinforced.

A fabricating method using the columnar spacer of the present inventionhaving the foregoing shape will be described below in brief. FIGS. 3A to3E are sectional views showing steps of the present invention, and FIG.4 is a flowchart showing the sequence of steps.

First, a first substrate 300 on which switching elements and pixelelectrodes are formed in matrix form, is prepared. Besides, a secondsubstrate 304 on which electrodes are formed, is prepared. Incidentally,in FIG. 3, for simplicity, the switching elements, the pixel electrodesand the like are not shown. Next, after alignment films 301 and 305 areformed on the first substrate 300 and the second substrate 304,respectively, a rubbing processing is performed (FIG. 3A).

Next, a spacer material layer 302 is formed on the alignment film 301 ofthe first substrate (FIG. 3B). Here, although an example in which acolumnar spacer is formed on the first substrate is described, a step offorming the columnar spacer on the second substrate may be adopted.

After a pattern of columnar spacers is exposed to the thus formed spacermaterial layer 302 through a mask for exposure, a development processingis performed and columnar spacers 303 are formed (FIG. 3C).

Then a sealing material pattern 306 is formed on the second substrate304 on which the electrodes and the alignment film 305 are formed. Inthe sealing material pattern, a pattern frame of forming a liquidcrystal injection port, having a rectangle shape and the same width, isformed. Here, although there is shown an example in which a sealingregion is formed on the second substrate, a step of forming a sealing,region on the first substrate may be adopted. Then the first substrate300 is bonded to the second substrate 304. A bonding step is a step inwhich after the substrates are bonded to each other with high accuracyby using an alignment mark, a sealing material is hardened bypressurizing and firing (FIG. 3D).

Thereafter, the first substrate and the second substrate are cut into asuitable size, and after a liquid crystal material 307 is injected fromthe liquid crystal injection port, the injection port is sealed. In thisway, a liquid crystal panel is completed.

In the foregoing steps, there is shown an example in which after thealignment film is formed on the first substrate, the columnar spacer isformed thereon. However, as shown in FIGS. 14A to 14E, such a step maybe adopted that after a columnar spacer 1102 is formed on a firstsubstrate 1100, an alignment film 1103 is formed thereon.

Besides, such a step may be adopted that a color filter or a shieldingfilm is formed on the first substrate or the second substrate.

Besides, here, although an example of an active matrix type liquidcrystal display device is shown, the invention is not particularlylimited. For example, the invention can also be applied to a simplematrix type liquid crystal display device, and a display system may beof a TN type or STN type, or a transmission type or reflection type.

The present invention made of the foregoing structure will be describedin more detail with embodiments described below.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1

An embodiment according to the present invention is described by usingFIGS. 5A to 8B. A method for fabricating a pixel section and a drivercircuit provided in its peripheral at the same time, is described here.Note that a CMOS circuit which is a basic circuit for a shift registerand buffer circuit etc., and an n-channel TFT forming a sampling circuitare shown for the driver circuit for the simplicity of explanation.

In FIG. 5A, it is preferable to use a glass substrate or a quartzsubstrate for substrate 501. Other than those, a silicon substrate, ametal substrate or a stainless steel substrate having an insulating filmformed on the surface thereof may be used. If heat resistivity permits,it is also possible to use a plastic substrate.

A base film 502 which comprises an insulating film comprising silicon(“an insulating film comprising silicon” generically represents asilicon oxide film, a silicon nitride film or a silicon oxynitride filmin the present Specification) is formed by plasma CVD or sputtering to athickness of 100 to 400 nm on a surface of the substrate 501 on whichthe TFTs are to be fabricated.

Through the Specification silicon oxynitride film is an insulating filmrepresented by SiOxNy and denotes an insulating film which comprisessilicon, oxygen and nitrogen at a prescribed proportion. In the presentEmbodiment a laminate film of a silicon oxynitride film of 100 nmthickness which contains nitrogen at 20 to 50 atomic % (typically 20 to30 atomic %) and a silicon oxynitride film of 200 nm thickness whichcontains nitrogen at 1 to 20 atomic % (typically 5 to 10 atomic %) isused as the base film 502. Note that the thickness need not be limitedto these values. The proportion of nitrogen and oxygen contained (atomic% proportion) in the silicon oxynitride film may be 3:1 to 1:3(typically 1:1). Note that the silicon oxynitride film may be fabricatedby using SiH₄, N₂O and NH₃ as raw material gases.

The base film 502 is disposed in order to prevent impurity contaminationfrom the substrate and may not be necessarily disposed in case of usinga quartz substrate.

A semiconductor film containing amorphous structure (amorphous siliconfilm in the present embodiment (not shown)) is formed on the base film502 to a thickness of 30 to 120 nm (preferably 50 to 70 nm) by a knownfilm deposition method. As a semiconductor film containing amorphousstructure, there are amorphous semiconductor film and microcrystallinesemiconductor film. Further, a compound semiconductor film containingamorphous structure such as amorphous silicon germanium film etc. mayalso be included. When the film was formed into the above statedthickness, the thickness of the active layer at the point of finallycompleting the TFT becomes 10 to 100 nm (preferably 30 to 50 nm).

A semiconductor film containing crystalline structure (crystallinesilicon film in embodiment 1) 503 is formed according to a techniquedisclosed in the Japanese Patent Application Laid-Open No. Hei 7-130652(corresponding to U.S. Pat. No. 5,643,826). The technique described inthe gazette is a crystallization means that uses a catalytic element forpromoting crystallization (one or plural of element selected fromnickel, cobalt, germanium, tin, lead, palladium, iron and copper;typically nickel) in crystallizing the amorphous silicon film.

More concretely, heat-treatment is conducted under the condition wherethe catalytic element(s) is held on the surface of the amorphous siliconfilm to convert the amorphous silicon film to the crystalline siliconfilm. Although the present Embodiment uses a technique described in theEmbodiment 1 of the gazette, a technique described in Embodiment 2 mayalso be used. Though single crystal silicon film and polycrystallinesilicon film are both included in crystalline silicon film, thecrystalline silicon film formed in the present embodiment is a siliconfilm having crystal grain boundaries. (FIG. 5A)

Though it depends on hydrogen content in the amorphous silicon film, itis preferable to carry out dehydrogenating process by heating at 400 to550° C. for some hours to reduce the contained hydrogen amount at 5 atom% or lower and conduct crystallization process. The amorphous siliconfilm may be fabricated by other deposition methods such as sputtering orevaporation, but it is preferable to sufficiently reduce impurityelements such as oxygen or nitrogen contained in the film.

Because the base film and the amorphous silicon film can be fabricatedby the same deposition method, they may be successively formed. Itbecomes possible to prevent contamination of the surface by not exposingto the atmosphere after formation of the base film, so that scatteringin the characteristics of the fabricated TFTs can be reduced.

Next, a light generated from a laser light source (laser light) isirradiated onto the crystalline silicon film 503 (hereinafter referredto as laser annealing) and a crystalline silicon film 504 in whichcrystallinity is improved is formed. Though a pulse oscillation type ora continuous oscillation type excimer laser light is preferable for thelaser light, a continuous oscillation type argon laser light may also beused as the laser light. The beam shape of the laser light may belinear, or it may be a rectangular shape. (FIG. 5B)

In place of laser light, a light generated from a lamp (hereinafterreferred to as lamp radiation) may be irradiated (hereinafter referredto as lamp annealing). As a lamp radiation, lamp radiation generatedfrom for instance halogen lamp or infrared lamp can be used.

Note that a process for performing heat treatment (annealing) by laserlight or lamp light as described here is referred to as a lightannealing process. Because light annealing process can perform hightemperature heat treatment in a short time, an effective heat treatmentprocess can be performed at high throughput even in case of using asubstrate that has a low heat resistance such as a glass substrate etc.Needless to say, they may be replaced by a furnace annealing usingelectric furnace (also referred to as thermal annealing) since theobject is annealing.

In the present Embodiment, laser annealing process was carried out byforming pulse oscillation type excimer laser light into a linear shape.The laser annealing conditions are: XeCl gas is used as excitation gas,treatment temperature is set at room temperature, pulse oscillationfrequency is set at 30 Hz, and laser energy density at 250 to 500 mJ/cm²(typically 350 to 400 mJ/cm²).

Laser annealing process carried out at the above stated conditions hasan effect of completely crystallizing the amorphous region remainedafter heat crystallization as well as reducing defects in thecrystalline region already crystallized. Accordingly, the presentprocess may be called a process for improving crystallinity of thesemiconductor film by light annealing, or a process for promotingcrystallization of the semiconductor film. It is also possible to obtainsuch effect by optimizing the conditions of lamp annealing. In thepresent Specification such condition is referred to as the first lightannealing condition.

Island semiconductor films (hereinafter referred to as active layers)505 to 508 are next formed by patterning the crystalline silicon film504. Note that alignment markers used for adjusting the position in thelater patterning are formed at the same time by using crystallinesilicon film. In the present Embodiment time required for separatelyforming alignment markers (increase in the number of masks) can be savedbecause alignment markers can be formed at the same time with theformation of active layers.

Next a protection film 509 is next formed over the active layers 505 to508 for later impurity doping. The protection film 509 uses a siliconoxynitride film or a silicon oxide film of 100 to 200 nm (preferably 130to 170 nm) thickness. This protection film 509 has a meaning of notexposing the crystalline silicon film directly to plasma in impuritydoping, and enabling trace concentration control. (FIG. 5C)

Then, a resist mask 510 is formed thereon, and impurity elementimparting p-type (hereinafter referred to as p-type impurity element) isdoped through protection film 509. As a p-type impurity element,typically an element which belongs to group 13 of periodic table, morespecifically, boron or gallium can be used. This process (referred to aschannel doping process) is a process for controlling threshold voltageof a TFT. Here, boron is doped by ion doping in which diborane (B₂H₆) isexcited by plasma without mass separation. Needless to say, it isacceptable to use ion implantation in which mass separation isperformed.

By this process, active layers 511 to 513 added with p-type impurityelement (boron in this Embodiment) at a concentration of 1×10¹⁵ to1×10¹⁸ atoms/cm³ (typically 5×10¹⁶ to 5×10¹⁷ atoms/cm³) are formed.These active layers 511 to 513 will later become active layers forn-channel TFTs. Note that the concentrations stated in the presentSpecification are measured values by SIMS (secondary ion massspectroscopy).

Note that through the specification, an impurity region containingp-type impurity region at least in the above stated concentration rangeis defined as a p-type impurity region (b) (however, regions whereimpurity elements imparting n-type typically phosphorus or arsenic aredoped at a concentration of 1×10¹⁶ atoms/cm³ are excluded). (FIG. 5D)

Resist mask 510 is next removed and new resist masks 514 a to 514 d areformed. Then impurity regions imparting n-type 515 to 517 are formed bydoping impurity element imparting n-type (hereinafter referred to asn-type impurity element). As an n-type impurity element, typically anelement belonging to group 15, more specifically, phosphorus or arseniccan be used. (FIG. 5E)

These low concentration impurity regions 515 to 517 are impurity regionsthat function as LDD regions in the n-channel TFT of the later formedCMOS circuit and sampling circuit. In thus formed impurity regions,n-type impurity element is contained at a concentration of 2×10¹⁶ to5×10¹⁹ atoms/cm³ (typically 5×10¹⁷ to 5×10¹⁸ atoms/cm³). In the presentspecification, an impurity region containing n-type impurity element inthe above stated concentration range is defined as an n-type impurityregion (b).

Note that phosphorus is doped here by ion doping to a concentration of1×10¹⁸ atoms/cm³ in which phosphine (PH₃) is excited by plasma withoutmass separation. Needless to say, ion implantation in which massseparation is performed may be used as well. In this process, phosphorusis doped into the crystalline silicon film through protecting film 509.

Next, resist masks 514 a to 514 d and a protecting film 509 are removed,and irradiation process by laser light is conducted again. Here againexcimer laser light of pulse oscillation type or continuous oscillationtype is preferable as the laser light, but argon laser light ofcontinuous oscillation type may also be used. The beam shape of thelaser light may be either of linear or rectangular shape. However,because activation of the doped impurity element is the object, it ispreferable to irradiate with an energy at a level of not melting thecrystalline silicon film. It is also possible to conduct laser annealingprocess with the protecting film 509 left thereon. (FIG. 5F)

In the present Embodiment, laser annealing process was carried out byforming pulse oscillation type excimer laser light into a linear shape.The laser annealing conditions are: KrF gas is used as excitation gas,treatment temperature is set at room temperature, pulse oscillationfrequency is set at 30 Hz, and laser energy density at 100 to 300 mJ/cm²(typically 150 to 250 mJ/cm²).

The light annealing process carried out on the above stated conditionshas an effect of recrystallizing the semiconductor film that was madeinto amorphous in impurity element doping as well as activating theimpurity element imparting n-type or p-type that was doped. It ispreferable that the above stated conditions make atomic arrangementcoordinated without melting the semiconductor film and at the same timeactivate the impurity elements. The present process may be referred toas a process for activating the impurity element imparting n-type orp-type by light annealing, a process for recrystallizing thesemiconductor film or a process for simultaneously carrying out both ofthem. Such effect can be obtained by optimizing the lamp annealingcondition as well. In the present specification, this condition isreferred to as the second light annealing condition.

By this process, the boundary of n-type impurity regions (b) 515 to 517,that is, the junction area with the intrinsic regions (p-type impurityregion (b) is also regarded as substantially intrinsic) that existaround n-type impurity region (b) become clear. This means that LDDregion and channel formation region may form a very good junction whenlater finishing TFT.

On activation of the impurity elements by this laser light, activationby heat treatment which uses an electric furnace may also be combined.In case of conducting activation by heat treatment, heat treatment ofapproximately 450 to 650° C. (preferably 500 to 550° C.) may beconducted considering the heat resistance of the substrate.

Next, gate insulating film 518 is formed to cover the active layers 505and 511 to 513. Gate insulating film 518 may be formed into a thicknessof 10 to 200 nm, preferably into 50 to 150 nm. In the presentembodiment, a silicon oxynitride film is formed into a thickness of 115nm by plasma CVD with raw materials of N₂O and SiH₄. (FIG. 6A)

Then, a conductive film, that will form a gate wiring is formed. Notethat the gate wiring may be formed by a single layered conductive film,but it is preferable to form laminated films of double layers, or triplelayers as occasion demands. In the present embodiment, laminatecomprising a first conductive film 519 and a second conductive film 520,is formed. (FIG. 6B)

As the first conductive film 519 and the second conductive film 520, ametal film comprising an element selected from tantalum (Ta), titanium(Ti), molybdenum (Mo), tungsten (W), chromium (Cr), niobium (Nb), andsilicon (Si), a metal compound film composed of these element as itsmain component (typically tantalum nitride film, tungsten nitride filmor titanium nitride film), an alloy film combining these elements(typically Mo—W alloy film, Mo—Ta alloy film, tungsten silicide film) ora laminate film of these thin films can be used.

The first conductive film 519 may be formed into 10 to 50 nm (preferably20 to 30 nm) and the second conductive film 520 may be formed into 200to 400 nm (preferably 250 to 350 nm). In the present Embodiment,tantalum nitride (TaN) film of 50 nm thick was used as the firstconductive film 519 and tantalum (Ta) film of 350 nm thick was used asthe second conductive film 520.

Other than this, a laminate of tungsten nitride film and tungsten film,a single layer of tantalum nitride film and a tungsten silicide film arealso appropriate. In addition, when a structure which has a silicon filmat a thickness of approximately 2 to 20 nm formed under the firstconductive film 519 (polycide structure) is employed, close adhesion ofconductive film formed on the silicon film is improved and oxidation ofthe conductive film can be prevented.

Further, it is effective to nitrificate by exposing the surface intoplasma atmosphere using ammonia gas or nitrogen gas, in case of using ametal film for the second conductive film 520 like in embodiment 1. Bydoing so, it is possible to prevent the oxidation of the surface of themetal film.

Gate wirings (they can also be referred to as gate electrodes) 521 to524 a and 524 b are formed into 400 nm thickness by etching the firstconductive film 519 and the second conductive film 520 at a time. Gatewirings 522 and 523 that are formed in a driver circuit are formed tooverlap a portion of n-type impurity region (b) 515 to 517 byinterposing a gate insulating film. Note that the gate wirings 524 a and524 b seem to be two electrodes in the cross sectional view, but ineffect they are formed of one continuing pattern. (FIG. 6C)

Then, n-type impurity element (phosphorus in the present Embodiment) isdoped in a self-aligned manner using gate electrodes 521 to 524 b asmasks. The concentration of phosphorus doped into thus formed impurityregions 525 to 530 are set at a concentration of ½ to 1/10 (specifically⅓ to ¼) of the above stated n-type impurity region (b) (provided it ishigher by 5 to 10 times than boron concentration added in the channeldoping process, specifically 1×10¹⁶ to 5×10¹⁸ atoms/cm³, typically3×10¹⁷ to 3×10¹⁸ atoms/cm³). In the present Specification, an impurityregion containing n-type impurity element at the above statedconcentration range is defined as n-type impurity region (c). (FIG. 6D)

Note that although boron is already doped into n-type impurity regions(c) 527 to 530 at a concentration of 1×10¹⁵ to 1×10¹⁸ atoms/cm³ in thechannel doping process, because phosphorus is doped at a concentrationof 5 to 10 times that of boron contained in the p-type impurity region(b), the effect of boron may be neglected.

Strictly speaking however, while concentration of phosphorus in portionsof n-type impurity region (b) 515 to 517 that overlapped with gatewirings remains at 2×10¹⁶ to 5×10¹⁹ atoms/cm³, portions that do notoverlap with gate wirings are further added with phosphorus of 1×10¹⁶ to5×10¹⁸ atoms/cm³, and contain phosphorus at a slightly higherconcentration.

Next, the gate insulating film 518 is etched in a self-aligned mannerwith gate electrodes 521 to 524 b as masks. Dry etching is used for theetching process and CHF; gas may be used as an etchant. Note that theetchant need not be limited to this material. Thus, gate insulatingfilms 531 to 534 a and 534 b under the gate wirings are formed. (FIG.6E)

By exposing the active layers in this manner, acceleration voltage inthe doping process of impurity elements next performed can be kept low.Accordingly throughput is increased since the necessary dose amount issmall. Needless to say, the impurity regions may also be formed bythrough doping without etching the gate insulating film.

Resist masks 535 a to 535 d are next formed to cover the gate wirings,and impurity regions 536 to 544 containing phosphorus at a highconcentration were formed by adding n-type impurity element (phosphorusin embodiment 1). Again ion doping (ion implantation is also acceptable)was conducted by utilizing phosphine (PH₃) and the phosphorusconcentration in these regions is set at 1×10²⁰ to 1×10²¹ atoms/cm³(specifically 2×10²⁰ to 5×10²¹ atoms/cm³). (FIG. 6F)

Note that in this Specification an impurity region containing n-typeimpurity element in the above stated concentration range is defined asn-type impurity region (a). Further, although phosphorus and boron,added in the preceding processes, are already contained in the impurityregions 536 to 544, influence of phosphorus or boron added in thepreceding processes need not be considered since phosphorus is lateradded at a sufficiently high concentration. Therefore, it is acceptableto refer the impurity regions 536 to 544 to as n-type impurity region(a) in this Specification.

Resist masks 535 a to 535 d are then removed, and new resist mask 545 isformed. Then, p-type impurity element (boron in the present embodiment)is doped, and impurity regions 546 and 547 that include boron at a highconcentration are formed. Here, boron is doped at a concentration of3×10²⁰ to 3×10²¹ atoms/cm³ (typically 5×10²⁰ to 1×10²¹ atoms/cm³) by iondoping using diborane (B₂H₆) (needless to say, ion implantation is alsoacceptable). In the present specification, an impurity region thatincludes p-type impurity region in the above stated concentration rangeis defined as p-type impurity region (a). (FIG. 7A)

Phosphorus is already doped in a portion of impurity regions 546 and 547(n-type impurity regions (a) 536 and 537 stated above) at aconcentration of 1×10²⁰ to 1×10²¹ atoms/cm³. However boron is doped at aconcentration higher by at least 3 times here. Therefore, already formedn-type impurity regions are totally inverted to p-type, and function asp-type impurity regions. Accordingly, it is acceptable to defineimpurity regions 546 and 547 as p-type impurity regions (a).

After removing resist mask 545, a first interlayer insulating film 548is formed. As a first interlayer insulating film 548, an insulating filmcomprising silicon, concretely a silicon nitride film, a silicon oxidefilm, a silicon oxynitride film or a laminate film combining these maybe formed. The film thickness may be 50 to 400 nm (preferably 100 to 200nm).

In the present embodiment a 200 nm thick silicon oxynitride film (notethat nitrogen concentration is 25 to 50 atomic %) is adopted, that isformed by plasma CVD from raw material gases of SiH₄, N₂O and NH₃. Thisfirst interlayer insulating film 548 has an effect of preventingincrease of resistivity due to oxidation of gate wiring 521 to 524 a and524 b in the next performed heat treatment process (activation process).

A heat treatment process is performed next in order to activate theimpurity elements of n-type or p-type conductivity and which have beendoped at their respective concentrations. Furnace annealing, laserannealing or rapid thermal annealing (RTA) can be performed for thisprocess. The activation process is performed by furnace annealing inembodiment 1. Heat treatment is performed in a nitrogen atmosphere atbetween 300 and 650° C., preferably from 400 to 550° C., here at 550° C.for 4 hours here. (FIG. 7B)

At this time, the catalytic element (nickel in embodiment 1) used incrystallization of an amorphous silicon film in embodiment 1 moved inthe direction of the arrows and is captured in a region containingphosphorus at a high concentration (gettering) formed in the process ofFIG. 6F. This is a phenomenon originated from gettering effect of ametal element by phosphorus. As a result, the concentration of thecatalytic element contained in later formed channel forming regions 549to 553 is reduced below 1×10¹⁷ atoms/cm³. Note however becauseconcentrations below 1×10¹⁷ atoms/cm³ is the detection limit of SIMS fornickel, it is impossible to measure with the present technology.

Conversely, the catalytic element precipitated at a high concentrationin the regions which functioned as gettering sights of the catalyticelement (regions where impurity regions 536 to 544 were formed in theprocess of FIG. 6F), and it existed in these regions at a concentrationexceeding 5×10¹⁸ atoms/cm³ (typically 1×10¹⁹ to 5×10²⁰ atoms/cm³).However since it is acceptable if the regions that became the getteringsights function as a source region or a drain region, it is presumedthat the existence of nickel do not cause any problem.

Further, a hydrogenation process is performed on the active layers byperforming heat treatment in an atmosphere containing 3 to 100% hydrogenat 300 to 450° C. for 1 to 12 hours. This is a process to terminatedangling bonds in the semiconductor layers by thermally activatedhydrogen. Plasma hydrogenation (using hydrogen activated by plasma) maybe performed as another hydrogenation means.

The second interlayer insulating film 554 is formed into 500 nm to 1.5mm thickness over the first interlayer insulating film 548 after theactivation process. In embodiment 1 a silicon oxide film having 800 nmthickness is formed by plasma CVD as the second interlayer insulatingfilm 554. Thus an interlayer insulating film of 1 mm thickness is formedfrom a laminate of the first interlayer insulating film (siliconoxynitride film) 548 and the second interlayer insulating film (siliconoxide film) 554.

Note that, it is possible to use organic resin insulating films such aspolyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene)for the second interlayer insulating film 554.

Contact holes are then formed in order to reach the source regions orthe drain regions of the respective TFTs, and source wirings 555 to 558,and drain wirings 559 to 562 are formed. Note that, although not shownin the figures, the drain wirings 559 and 560 are formed from the samewiring in order to form a CMOS circuit. Note that, in embodiment 1 theelectrodes are made with a three-layer structure laminate film of a 100nm Ti film, a 300 nm aluminum film containing Ti, and a 150 nm Ti filmformed successively by sputtering.

A silicon nitride film, a silicon oxide film, or a silicon oxynitridefilm is formed to a thickness of between 50 and 500 nm (typically 200 to300 nm) next as a passivation film 563. (FIG. 7C)

It is effective to perform a plasma treatment using a gas that containshydrogen such as H₂ and NH₃ preceding formation of the film and toperform heat treatment after the film formation. The preceding processprovides excited hydrogen into the first and second interlayerinsulating films. By performing a heat treatment to this state, theactive layers are effectively hydrogenated because hydrogen added intothe first and second interlayer insulating films is diffused in thelayer underneath, as well as improving the film quality of passivationfilm 563.

Further, after forming the passivation film 563, an additionalhydrogenation process may be performed. For example, it is good toperform heat treatment for 1 to 12 hours at between 300 and 450° C. inan atmosphere including from 3 to 100% hydrogen. Or, a similar resultcan be obtained by using plasma hydrogenation.

Note that openings may be formed here in the passivation film 563 atpositions where contact holes will be formed later in order to connectthe pixel electrode and the drain wirings.

A third interlayer insulating film 564 (in the present specification itis occasionally referred to as planarization film) comprising a resinmaterial (it may also be referred to as organic material) (hereinafterreferred to as resin insulating film) is formed with an approximately 1to 3 μm (typically 1.5 to 2 μm), as shown in FIG. 7D.

Polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutane),or Cyclotene, can be used as the resin material. The following pointscan be given as the benefits of using a resin insulating film: superiorlevelness; and low dielectric constant. Note that in addition to theabove, other organic resin insulating films, organic SiO compounds, etc.can be used. It is possible to use an insulating film comprisinginorganic material if the superior in flatness.

Note that though an acrylic film which polymerizes by heat afterapplication to the substrate is used here, one that polymerizes by lightradiation may also be used. Needless to say, a photo sensitive materialof positive type or negative type is also acceptable.

Further, it is possible to provide a resin film colored by pigment etc.as a part of layer of the third interlayer insulating film 564 and useis as the color filter.

A shielding film 565 is formed next on the third interlayer insulatingfilm (planarization film) 564 comprising resin material in the pixelsection. A term “shielding film” is used through the specification to aconductive film which has a characteristic of shielding light orelectromagnetic wave.

The shielding film 565 is formed from a metallic film comprising anelement selected from among aluminum (Al), titanium (Ti), and tantalum(Ta) or a metal film with one of these as its principal constituent (inthe present embodiment an element is regarded as the principalconstituent when it is contained at over 50 weight %) to a thicknessbetween 100 and 300 nm. In the present Embodiment an aluminum filmcontaining titanium at 1 wt % is formed into 125 nm thick. Note that insome cases this shielding film is referred to as “first conductive film”in the present specification.

Note that a silicon oxide film is formed to a thickness of 5 to 50 nm(typically 20 to 30 nm) prior to forming the shielding film 565. Theshielding film 565 is then formed thereon and a silicon oxide filmdenoted as 566 is formed by performing etching treatment onto the abovestated insulating film as the shielding film 565 as a mask.

Though the silicon oxide film 566 is disposed to increase adhesivenessof the third interlayer insulating film 564 and the shielding film 565,it is preferable to remove it from the region where the shielding filmdoes not exist, because it will be a hindrance in forming a contact holein the third interlayer insulating film. Note that the adhesiveness tothe shielding film formed on this film can be increased by surfacerefinement also by performing plasma processing using CF₄ gas on thesurface of the third interlayer insulating film 564.

Further, it is possible to form other connecting wirings, not only theshielding film, by using the aluminum film containing titanium. Forexample, a connecting wiring for connecting between circuits can beformed inside the driver circuit. However, in this case, beforedepositing the material that forms the shielding film or the connectingwiring, it is necessary to form contact holes, in advance, in the thirdinterlayer insulating film.

Next, an oxide with a thickness from 20 to 100 nm (preferably between 30and 50 nm) is formed on the surface of the shielding film 565 bypublicly known anodic oxidation or plasma oxidation (Anodic oxidation inthe present embodiment). An aluminum oxide film (alumina film) is formedhere as the anodic oxide 567 because a film with aluminum as itsprincipal constituent is used as the shielding film 565 and anodicoxidation is performed in embodiment 1. This anodic oxide 567 will be adielectric for the storage capacitor of the present embodiment.

Further, the structure used here has the insulator being formed byanodic oxidation only on the surface of the shielding film, but otherinsulator may also be formed by a gas phase method, such as plasma CVD,thermal CVD, or sputtering. In that case also, it is preferable to makethe film thickness from 20 to 100 nm (more preferably between 30 and 50nm).

Contact holes are formed next in the third interlayer insulating film564 and in the passivation film 563 in order to reach the drain wiring562, and the pixel electrode 569 is formed. Note that pixel electrodes570 and 571 are each separate pixel electrodes for adjoining pixels inthis embodiment. A transparent conductive film may be used for the pixelelectrodes 569 to 571, in concrete, indium tin oxide (ITO) film with athickness of 110 nm is formed here by sputtering. Note that there arecases in which the pixel electrode is referred to as the “secondconductive film” in the present specification.

Note that a metallic film may be used as the material for the pixelelectrode in case of forming a reflection type liquid crystal displaydevice.

Further, a storage capacitor 572 is formed at this point where the pixelelectrode 569 and the shielding film 565 overlap through the anodicoxide film 567. Note that though only the storage capacitor 572 isnumbered, all regions where the shielding film and the pixel electrodeoverlaps functions as a storage capacitor.

Because an alumina film which has a high dielectric constant of 7 to 9is used as the dielectric of the storage capacitor, reduction of thearea for forming a required capacitance is available. Further, by usingthe shielding film which is formed over that pixel TFT as an electrodeof the storage capacitor, the aperture ratio of the image displaysection of an active matrix liquid crystal display device can beincreased.

In this case it is preferable to set the shielding film 565 at floatingstate (electrically isolated state) or a constant electric potential,more preferably at a common electric potential (median electricpotential of image signals sent as data).

Through the foregoing steps, an active matrix substrate (firstsubstrate) on which the pixel TFT and the pixel electrode were formed,was formed.

Next, steps of forming an active matrix type liquid crystal displaydevice from the active matrix substrate (first substrate) will bedescribed. First, an alignment film 573 was formed on the firstsubstrate on which the pixel TFT and the pixel electrode were formed. Atransparent conductive film 575 and an alignment film 576 were formed onan opposite substrate (second substrate) 574. A color filter or ashielding film may be formed on the second substrate as needed. In thisembodiment, a polyimide film is used as the alignment film. After thealignment film 573 was applied by a roll coater, it was heated at 200°C. for 90 minutes. Incidentally, it is preferable that the firstsubstrate is washed before the alignment film 573 is formed. Thereafter,the surface of the alignment film was rubbed with a roller on which acloth was fixed, and a rubbing orientation processing was performed sothat liquid crystal molecules were oriented with a constant pretiltangle (6° to 10°, preferably 7° to 8°).

Next, photosensitive acryl resin (NN700: made by JSR), as a spacermaterial layer, was spin coated on the alignment film 573 at 900 rpm sothat its thickness was made 4.7 μm. Thereafter, heating at 80° C. for 3minutes was carried out by using a hot plate. The thickness of thephotosensitive acryl resin film after heating was made 4.0 μm.

After a pattern (size: 6 μm square) of a columnar spacer was exposed tothe thus formed spacer material layer through a mask for exposure,development was made. The development conditions were made such thatCD-700 (TMAH 0.14%) was used as a developing solution, solutiontemperature was made 18±1° C., and a development time was made 60seconds. Next, heating at 180° C. for 1 minute was carried out using aclean oven.

In this way, a columnar spacer 568 was formed on the first substrate(FIG. 8A). Since the formation position of the columnar spacer 568 canbe freely designed, an image display region can be effectively used.Incidentally, the pretilt angle was changed to 4° to 5° through thedeveloping solution.

FIG. 12 is a view showing a pixel structure of this embodiment seen fromthe above. As shown in FIG. 12, in this embodiment, a columnar spacer 63is provided over a contact portion 65 where a pixel TFT is electricallyconnected to a pixel electrode 62. Besides, in FIG. 12, referencenumeral 565 designates a shielding film, and the pixel electrode 62 isprovided thereon through a not-shown oxide 567. At this time, storagecapacitances 64 a to 64 c are formed of the shielding film 565, theoxide 567, and the pixel electrode 62. By adopting the structure of thisembodiment, it becomes possible to fill a stepped portion (correspondingto the film thickness of the interlayer insulating film 564) formed atthe contact portion, and defective orientation in liquid crystalmolecules due to the stepped portion can be prevented.

Like this, in this embodiment, there is shown an example in which thecolumnar spacer is formed over the contact portion of the TFT and thepixel electrode. However, as long as the columnar spacer 568 is formedat a region which is not used as an image display region, such as aregion on a shielding film or a source wiring, the position is notparticularly limited. In this embodiment, the columnar spacers wereregularly disposed at the pixel portion at a rate of about 100 spacersper 1 mm². FIG. 17A is a view of an SEM observation photograph of asection of the columnar spacer of this embodiment. FIG. 1A is a view ofan SEM observation photograph showing its outer appearance. FIG. 2A is aschematic view showing its arrangement, and FIGS. 2B and 2C are SEMobservation photographs corresponding to FIG. 1A and having differentmagnifications.

The shape of this columnar spacer was such that there was little taperportion, the top portion had a flat surface, the height H was 4 μm, thewidth L1 was 6 μm, and the radius of curvature was 1 μm or less. Theangle α between the tangent plane at the center of a side of thecolumnar spacer and the substrate surface was 85° to 95°, and it wasalmost vertical. By making such a shape, light leakage can be decreased.

Then the active matrix substrate on which the pixel portion and thedriver circuit are formed is bonded to the opposite substrate by awell-known cell assembling step through a sealing material 579. In thisembodiment, the substrate interval was kept constant by using thesealing material containing a filler 580. Besides, in this embodiment,since the columnar spacer 568 made of a resin material with excellentelasticity is used, pressure applied at the bonding step can be absorbed(relieved). Besides, in the spacer of this embodiment, since a contactarea to an element is larger than that of a bead-like spacer, there doesnot occur such a case where an excessive pressure is applied to aspecific portion.

Thereafter, a liquid crystal 578 is injected between both thesubstrates, and they are completely sealed by a sealant (not shown). Awell-known liquid crystal material may be used for the liquid crystal.In this way, the active matrix type liquid crystal display device shownin FIG. 8B is completed.

Incidentally, in FIG. 8B, a p-channel TFT 701 and n-channel TFTs 702 and703 are formed in the driver circuit, and a pixel TFT 704 made of ann-channel TFT is formed in the pixel portion.

Incidentally, the sequence of the steps of this embodiment may besuitably changed. Even if any sequence is adopted, if the structure of afinally formed TFT is a structure as shown in FIG. 8B, the basicfunction of the active matrix substrate is not changed, and the effectof the present invention is not spoiled.

A channel forming region 601, a source region 602 and a drain region 603are each formed by a p-type impurity region (a) in the p-channel TFT 701of the driver circuit. Note that a region that contains phosphorus at aconcentration of 1×10²⁰ to 1×10²¹ atoms/cm³ exists in a portion of asource region or a drain region in effect. Further in that region thecatalytic element gettered in the process of FIG. 7B exists at aconcentration exceeding 5×10¹⁸ atoms/cm³ (typically 1×10¹⁹ to 5×10²⁰atoms/cm³).

Further, a channel forming region 604, a source region 605, and a drainregion 606 are formed in the n-channel TFT 702, and a LDD regionoverlapping with the gate wiring by interposing a gate insulating film(such region is referred to as Lov region. ‘ov’ means overlap) 607 isformed in one side of the channel forming region (drain region side).Here, Lov region 607 contains phosphorus at a concentration of 2×10¹⁶ to5×10¹⁹ atoms/cm³, and is formed to completely overlap with the gatewiring.

A channel forming region 608, a source region 609, and a drain region610 are formed in the n-channel TFT 703. LDD regions 611 and 612 areformed in both sides of the channel forming region. Note that the LDDregions overlapping with the gate wiring by interposing an insulatingfilm (Lov regions) and the LDD regions that are not overlapped with thegate wiring (such region is referred to as Loff regions. ‘off’ meansoffset) are realized because a portion of the LDD regions 611 and 612are placed so as to overlap with the gate wiring in this structure.

A cross sectional view shown in FIG. 9 is an enlarged diagram showingn-channel TFT 703 shown in FIG. 8B in the state of being manufactured tothe process of FIG. 7B. As shown here, LDD region 611 is furtherclassified into Lov region 611 a and Loff region 611 b, and LDD region612 is further classified into Lov region 612 a and Loff region 612 b.Phosphorus is contained in the Lov regions 611 a and 612 a at aconcentration of 2×10¹⁶ to 5×10¹⁹ atoms/cm³, whereas it is contained ata concentration 1 to 2 times as much (typically 1.2 to 1.5 times) in theLoff regions 611 b and 612 b.

Further, channel forming regions 613 and 614, a source region 615, adrain region 616, Loff regions 617 to 620, and an n-type impurity region(a) 621 contacting the Loff regions 618 and 619 are formed in the pixelTFT 704. The source region 615, and the drain region 616 are each formedfrom n-type impurity region (a) here, and the Loff regions 617 to 620are formed by n-type impurity region (c).

The structure of the TFTs forming each of the circuits or elements ofthe pixel section and the driver circuits can be optimized to correspondto the required circuit specifications, and the operation performance ofthe semiconductor device and its reliability can be increased in thepresent embodiment. Specifically, the LDD region placement in ann-channel TFT is made to differ depending upon the circuitspecifications, and by using an Lov region or an Loff region properly,TFT structures with fast operating speeds and which place greatimportance on measures to counter hot carriers, and TFT structures thatplace great importance on low off current operation, can be realizedover the same substrate.

For the case of an active matrix liquid crystal display device, forexample, the n-channel TFT 702 is suitable for driver circuits thatplace great importance on high operating speed, such as a shift registercircuit, a signal divider circuit, a level shifter circuit, and a buffercircuit. In other words, by placing the Lov region in only one side (thedrain region side) of the channel forming region, this becomes astructure that reduces the resistive constituents as much while placinggreat importance on hot carrier countermeasures. This is because, forthe case of the above circuit group, the source region and the drainregion functions do not change, and the carrier (electron) movementdirection is constant. However, if necessary, Lov regions can be placedin both sides of the channel forming region.

Further, the n-channel TFT 703 is suitable for a sampling circuit(sample and hold circuit) which places emphasis on both hot carriercountermeasures and low off current operation. In other words, hotcarrier countermeasures can be realized by placement of the Lov region,and in addition, low off current operation is realized by placement ofthe Loff region. Furthermore, the functions of the source region and thedrain region of a sampling circuit reverse, and the carrier movementdirection changes by 180°; therefore a structure that has linearsymmetry with the center of the gate wiring must be used. Note that itis possible to only form the Lov region, depending upon thecircumstances.

Further, the n-channel TFT 704 is suitable for a pixel section or asampling circuit (sample and hold circuit) which place great importanceon low off current operation. Namely, the Lov region, which is a causeof an increase in the off current value, is not employed, only the Loffregion is used, allowing low off current operation to be realized.Furthermore, by utilizing a LDD region with a concentration lower thanthat of the driver circuit LDD region as the Loff region, although theon current value will fall a little, it is a thorough measure forlowering the off current value. Additionally, it has been confirmed thatan n-type impurity region (a) 621 is extremely effective in lowering theoff current value.

Further, the length (width) of the Lov region 607 of the n-channel TFT702 may be between 0.1 and 3.0 μm, typically from 0.2 to 1.5 μm.Further, the length (width) of the Lov regions 611 a and 612 a of then-channel TFT 703 may be from 0.1 to 3.0 μm, typically between 0.2 and1.5 μm, and the length (width) of the Loff regions 611 b and 612 b maybe from 1.0 to 3.5 μm, typically between 1.5 and 2.0 μm. Moreover, thelength (width) of the Loff regions 617 to 620 formed in the pixel TFT704 may be from 0.5 to 3.5 μm, typically between 2.0 and 2.5 μm.

The structure of the above stated active matrix liquid crystal displaydevice is described with reference to the perspective view of FIG. 10.An active matrix substrate (the first substrate) comprises a pixelportion 802, a driver circuit 803 on the gate side, and a driver circuit804 on the source side formed over a glass substrate 801. A pixel TFT805 in the pixel portion (which corresponds to the pixel TFT 704 shownin FIG. 8B) is an n-channel TFT, and is connected with a pixel electrode806 and a storage capacitor 807 (which corresponds to the storagecapacitor 572 shown in FIG. 8A).

The driver circuits provided on the periphery are formed based on a CMOScircuit. The driver circuit 803 on the gate side and the driver circuit804 on the source side are connected to the pixel portion 802 through agate wiring 808 and a source wiring 809, respectively. An externalinput/output terminal 811 connected with an FPC 810 is provided withinput/output wirings (connecting wirings) 812 and 813 for transmittingsignals to the driver circuits. Reference numeral 814 denotes anopposing substrate (the second substrate).

It is to be noted that, though the semiconductor device illustrated inFIG. 10 is herein referred to as an active matrix liquid crystal displaydevice, a liquid crystal panel having an FPC attached thereto such asthe one illustrated in FIG. 10 is generally referred to as a liquidcrystal module. Accordingly, the active matrix liquid crystal displaydevice in the present embodiment may also be referred to as a liquidcrystal module.

FIG. 11 shows an example of circuit structure of the above stated liquidcrystal display device. The liquid crystal display device of the presentembodiment comprises a source side driver circuit 901, a gate sidedriver circuit (A) 907, a gate side driver circuit (B) 911, a pre-chargecircuit 912 and a pixel section 906. Through the Specification, drivercircuit is a generic name including a source side driver circuit and agate side driver circuit.

The source side driver circuit 901 is provided with a shift registercircuit 902, a level shifter circuit 903, a buffer circuit 904, and asampling circuit 905. Further, the gate side driver circuit (A) 907 isprovided with a shift register circuit 908, a level shifter circuit 909,and a buffer circuit 910. The gate side driver circuit (B) 911 has asimilar structure.

The driver voltages for the shift register 902 and 908 is between 5 and16 V here (typically 10 V), and the structure shown by reference numeral702 in FIG. 8B is suitable for n-channel TFTs used in the CMOS circuitsforming the circuits.

Furthermore, the driver voltage becomes high at between 14 and 16 V forthe level shifter circuit 903 and 909, and the buffer circuit 904 and910, but similar to the shift register circuits, CMOS circuitscomprising the n-channel TFT 702 shown in FIG. 8B are suitable. Notethat using a multi-gate structure, such as a double gate structure and atriple gate structure for the gate wiring is effective in increasingreliability in each circuit.

Further, the sampling circuit 905 has a driver voltage of between 14 and16 V, but the source region and the drain region are inverted and it isnecessary to reduce the off current value, so CMOS circuits comprisingthe n-channel TFT 703 of FIG. 8B are suitable. Note that only then-channel TFT is shown in FIG. 8B, but in practice the n-channel TFT anda p-channel TFT are combined when forming the sampling circuit.

Further, the pixel section 906 has a driver voltage of between 14 and 16V, but it is necessary to reduce the off current value even lower thanthat of the sampling circuit 905. Therefore it is preferable to use astructure in which Lov region that causes increase in off current is notdisposed, and it is preferable to use n-channel TFT 704 of FIG. 8B forthe pixel TFT.

Embodiment 2

In this embodiment, an example in which a columnar spacer is provided ata place other than a sealing region and mechanical strength isreinforced, will be described with reference to FIGS. 13A and 13B. Thisembodiment shows a region (external terminal connection portion) whichis not shown in FIG. 8B of the embodiment 1. Thus, the drawingcorresponds to FIG. 8B of the embodiment 1 and the same referencesymbols are partially used. Incidentally, the only point different fromthe embodiment 1 is that a filler is not shown in a sealing material1000.

FIG. 13A is a top view of the external terminal connection portion, andFIG. 13B is a sectional structural view of the external terminalconnection portion. Besides, a sectional structure taken along d-d′ ofthe top view is also shown.

In FIGS. 13A and 13B, reference numeral 1001 designates a columnarspacer; 1002, an external terminal connection portion; 1003, an ITOfilm; 1004, a conductive spacer; 1005, an adhesive; and 1006, an FPC.

The external terminal connection portion 1002 connected to the FPC 1006extends from a source electrode (wiring) of a p-channel TFT 701.

In this embodiment, the columnar spacer 1001 is formed between a sealingregion where the sealing material 1000 exists and an end portion of anopposite substrate 574. This columnar spacer 1001 is provided betweenextraction wirings, and reinforces the mechanical strength. Besides,this columnar spacer 1001 has an effect to prevent cutting defects alsoin a cutting step of the opposite substrate. Incidentally, here, thewiring between the source electrode of the p-channel TFT 701 and theexternal terminal connection portion is called the extraction wiring.

This columnar spacer can be formed in the same step as that formed atthe contact portion in the embodiment 1.

The ITO film 1003 is formed on the external terminal connection portion1002 in the same step as the pixel electrode, and excellent contact withthe FPC is formed. Incidentally, a conductive spacer such as a goldpaste is mixed in the adhesive 1005, and the FPC 1006 is connected tothe ITO film 1003 by clamping.

Embodiment 3

In this embodiment, a description will be made on an example in which acolumnar spacer is formed by a following method (FIGS. 14A to 14E aresimplified step views, and FIG. 15 is a flowchart) different from theembodiment 1. In this embodiment, step sequence is different from theembodiment 1, and a columnar spacer is formed before formation of analignment film.

A procedure will be described in brief with reference to FIGS. 14A to14E. First, a spacer material layer 1101 is formed on a first substrate1100 (FIG. 14A). Next, similarly to the embodiment 1, exposure anddevelopment are performed, so that columnar spacers 1102 are formed(FIG. 14B). Next, an alignment film 1103 covering the columnar spacer1102 is formed, and a rubbing processing is performed (FIG. 14C). Next,a second substrate 1104 on which an alignment film 1105 and a seal 1106are formed is bonded to the first substrate 1100 (FIG. 14D). Next, thefirst substrate and the second substrate are cut into a suitable shape,a liquid crystal material 1107 is injected, and sealing is made, so thata liquid crystal panel is completed (FIG. 14E).

The details will be described below.

First, similarly to the embodiment 1, an active matrix substrate (firstsubstrate) is formed. The exact same steps were used until a step offorming pixel electrodes 569 and 570. Next, a columnar spacer 1201 wasformed on the first substrate by using the same spacer material as theembodiment 1 and under the same conditions (film formation condition,exposure condition, development condition, baking condition, etc.).

Next, an alignment film 1202 was formed to cover the columnar spacer(FIG. 16A). Thereafter, a rubbing processing was performed. In thefollowing, in the same way as the embodiment 1 except for these steps, aliquid crystal display device shown in FIG. 16B was formed.

FIG. 17B is a view of an SEM observation photograph of a section of thecolumnar spacer of this embodiment.

The shape of this columnar spacer was such that although a taper portionexisted, a top portion had a flat surface, the width L1 was 7 to 8 μm,and the radius of curvature was 2 μm. The angle α between the tangentplane at the center of a side of the columnar spacer and the substratesurface was 68°. In this embodiment, the value of the width L1 includesthe thickness of the alignment film. In this embodiment, when therelation between the widths is made 1≦L2/L1≦2.5, light leakage at thetaper portion can be decreased, so that it is desirable.

In the embodiment 1, the final pretilt angle was 4° to 5° by theinfluence of the developing solution. In this embodiment, since thealignment film is formed and the rubbing processing is performed afterthe columnar spacer is formed, the pretilt angle can be made 6° to 10°,preferably 7° to 8°, so that the orientation of liquid crystal can bemade excellent.

Incidentally, this embodiment can be combined with the embodiment 2.

Embodiment 4

In this embodiment, a description will be made on an example in whichcolumnar spacers are provided at a constant interval on the wholesurface of a first substrate as shown in FIG. 18A.

In FIG. 18A, reference numeral 1300 designates a sealing material; 1301,a first substrate; 1302, a pixel portion; 1303, a gate side drivercircuit; 1304, a source side driver circuit; 1305, a signal dividingcircuit; 1306, an external connection terminal portion; 1308,

In this embodiment, columnar spacers 1307 were provided between thepixel portion and the source side driver circuit, columnar spacers 1309were provided at the external connection terminal portion, columnarspacers 1310 were provided at the pixel portion, columnar spacers 1311were provided at the gate side driver circuit, and columnar spacers 1312were provided at the sealing region. The columnar spacers wererespectively provided at a constant interval by a photolithographymethod. By providing the columnar spacers at a constant interval likethis, a uniform substrate interval can be maintained. Besides, byproviding the columnar spacers 1312 at the sealing region, a filler maynot be used. Besides, by providing the columnar spacers 1309 at theexternal connection terminal portion, the mechanical strength at theconnection portion can be reinforced. Incidentally, the foregoingrespective columnar spacers may be formed by using the fabricatingmethod shown in the embodiment 1 or the embodiment 3.

FIG. 18B schematically shows a sectional structure of a region encircledby a dotted line 1322 in FIG. 18A. The same reference symbols as thoseof FIG. 18A are used. In FIG. 18A, reference numeral 1314 designates aCMOS circuit; 1315, an n-channel TFT; 1316, a pixel TFT; 1317, aninterlayer insulating film; 1318 a, a pixel electrode; and 1318 b, anITO film. The ITO film 1318 b is provided to be connected to an externalterminal such as an FPC. Besides, reference numeral 1319 designates aliquid crystal material; and 1320, an opposite electrode.

FIGS. 19A to 19C show other forms of spacer arrangement. FIG. 19A showsan example in which columnar spacers 1407 are uniformly formed inside asealing region 1408. FIG. 19B shows an example in which a columnarspacer is not provided at a pixel portion but columnar spacers 1410 areprovided at a sealing region and columnar spacers 1409 are provided atan external connection terminal portion. FIG. 19C shows an example inwhich columnar spacers 1411 and 1412 are formed at regions other than asealing region. Incidentally, the foregoing respective columnar spacersmay be formed by using the fabricating method shown in the embodiment 1or the embodiment 3.

Incidentally, this embodiment can be freely combined with theembodiments 1 to 3.

Embodiment 5

In the present Embodiment an active matrix substrate (the firstsubstrate) different from that of Embodiment 1 is manufactured. Notethat the processes described in the Japanese Patent Application No. Hei11-104646 is used for the details of the TFT manufacturing processes.

A low-alkaline glass substrate or a quartz substrate can be used as asubstrate 1501. On the surface of this substrate 1501 on which TFTs areto be formed, a base film 1502 such as a silicon oxide film, a siliconnitride film or a silicon oxynitride film is formed in order to preventthe diffusion of impurities from the substrate 1501.

Next, a semiconductor film that has an amorphous structure and athickness of 20 to 150 nm (preferably, 30 to 80 nm) is formed by a knownmethod such as plasma CVD or sputtering. In this embodiment, anamorphous silicon film was formed to a thickness of 55 nm by plasma CVD.Then, by a known crystallization technique, a crystalline silicon filmis formed from the amorphous silicon film. For example, a lasercrystallization method or a thermal crystallization method (solid phasegrowth method) may be applied, however, here, in accordance with thetechnique disclosed in Japanese Patent Application Laid-Open No. Hei7-130652, the crystalline silicon film was formed by the crystallizationmethod using a catalytic element.

Then, the crystalline silicon film is divided into islands, wherebyisland semiconductor layers are formed. Thereafter, a mask layer of asilicon oxide film is formed to a thickness of 50 to 100 nm by plasmaCVD or sputtering. Then, a resist mask is provided, and onto the wholesurfaces of the island semiconductor layers forming the n-channel TFTs,boron (B) was added as an impurity element imparting p-typeconductivity, at a concentration of about 1×10¹⁶ to 5×10¹⁷ atoms/cm³,for the purpose of controlling the threshold voltage. Next, in order toform the LDD regions of the n-channel TFTs in the driver circuit, animpurity element imparting n-type conductivity is selectively added tothe island semiconductor layers. For this purpose, resist masks wereformed in advance. Next, the mask layers are removed by hydrofluoricacid or the like, and the step of activating the added impurity elementsis carried out. The activation can be carried out by performing heattreatment in a nitrogen atmosphere at 500 to 600° C. for 1 to 4 hours orby using the laser activation method. Further, both methods may bejointly performed. In this embodiment, a laser activation method wasemployed.

Then, a gate insulator film 1520 is formed of an insulator filmcomprising silicon to a thickness of 10 to 150 nm, by plasma CVD orsputtering. Next, a conductive layer (A) comprising a conductive metalnitride film and a conductive layer (B) comprising a metal film arelaminated. The conductive layer (B) may be formed of an element selectedfrom among tantalum (Ta), titanium (Ti), molybdenum (Mo) and tungsten(W) or an alloy comprised mainly of the above-mentioned element, or analloy film (typically, an Mo—W alloy film or an Mo—Ta alloy film)comprised of a combination of the above-mentioned elements, while theconductive layer (A) comprises tantalum nitride (TaN), tungsten nitride(WN), titanium nitride (TiN), or molybdenum nitride (MoN). In thisembodiment, as the conductive layer (A), a tantalum nitride film with athickness of 30 nm was used, while, as the conductive layer (B), a Tafilm with a thickness of 350 nm was used, both films being formed bysputtering.

Next, resist masks are formed, and the conductive layer (A) and theconductive layer (B) are etched together to form gate electrodes 1528 to1531 and a capacitor wiring, 1532.

Then, in order to form the source region and the drain region of thep-channel TFT in the driver circuit, the step of adding an impurityelement imparting, p-type conductivity is carried out. Here, by usingthe gate electrode 1528 as a mask, impurity regions are formed in aself-alignment manner. In this case, the region in which the n-channelTFT will be formed is coated with a resist mask in advance.

Next, in the n-channel TFTs, impurity regions that functioned as sourceregions or drain regions were formed.

Then, the step of adding an impurity imparting n-type for formation ofthe LDD regions of the n-channel TFT in the pixel matrix circuit wascarried out. Thereafter, in order to activate the impurity elements,which were added at their respective concentrations for imparting n-typeor p-type conductivity, an activation process was performed by furnaceannealing in a nitrogen atmosphere. By this heat treatment of theactivation process performed here, the catalytic element could begettered from the channel-forming region of the n-channel and thep-channel TFTs. In this heat treatment metal nitride layers are formedon the surfaces of the gate wirings 1528 to 1531 and the capacitancewiring 1532 which exists over an impurity region 1527 with the gateinsulating film 1520 interposed therebetween. Further, a hydrogenationprocess of the island semiconductor layers is performed.

After the activation and hydrogenation steps are over, gate wirings 1547and 1548, and capacitance wiring 1549 was formed.

A first interlayer insulating film 1550 is formed of a silicon oxidefilm or a silicon oxynitride film with a thickness of 500 to 1500 nm,and contact holes reaching the source regions or the drain regions,which are formed in the respective island semiconductor layers, areformed; and source wirings 1551 to 1554 and drain wirings 1555 to 1558are formed. Next, as a passivation film 1559, a silicon nitride film, asilicon oxide film or a silicon oxynitride film is formed to a thicknessof 50 to 500 nm (typically, 100 to 300 nm).

Thereafter, a second interlayer insulating film 1560 comprised of anorganic resin is formed to a thickness of 1.0 to 1.5 μm. Then, a contacthole reaching the drain wiring 1558 in contact with drain region 1526 isformed in the second interlayer insulating film 1560, and pixelelectrodes 1561 and 1562 are formed. The pixel electrodes can be formedby using a transparent conductive film in the case a transmission typeliquid crystal display device is to be obtained, while, in the case areflection type liquid crystal display device is to be fabricated, thepixel electrodes can be formed by a metal film.

Next, a columnar spacer 1607 is formed. Since the step of forming thecolumnar spacer 1607 is the same as the spacer fabricating step of theembodiment 3, its explanation is omitted. Next, similarly to theembodiment 3, an alignment film 1601 covering the columnar spacer 1607is formed. After the alignment film is formed, a rubbing processing isperformed so that the liquid crystal molecules are oriented at aconstant pretilt angle (6° to 10°, preferably 7° to 8°). Alight-shielding film 1603, a transparent conductive film 1604, and analignment film 1605 are formed on an opposite substrate 1602 at theopposite side. An active matrix substrate on which a pixel matrixcircuit and a CMOS circuit are formed is bonded to the oppositesubstrate by a well-known cell assembling step. Thereafter, a liquidcrystal material 1606 is injected between both the substrates, andcomplete sealing is made by a sealant (not shown). An well-known liquidcrystal material may be used for the liquid crystal material. In thisway, an active matrix type liquid crystal display device shown in FIG.20 is completed.

In FIG. 20, a p-channel TFT 1701, a first n-channel TFT 1702, and asecond n-channel TFT 1703 are formed in the driver circuit, and a pixelTFT 1704 and a storage capacitance 1705 are formed in a display region.

Incidentally, this embodiment can be freely combined with theembodiments 1 to 4.

Embodiment 6

In this embodiment, a description will be made on an example in which adisplay device is fabricated by using a TFT different from the aboveembodiment.

In the above embodiment, although a top-gate type TFT is used, in thisembodiment, a first substrate is fabricated by using a bottom-gate typeTFT.

In FIG. 21, reference numeral 1814 designates a CMOS circuit; 1815, ann-channel TFT; 1816, a pixel TFT; 1817, an interlayer insulating film;1818 a, a pixel electrode; and 1818 b, an ITO film. This ITO film 1818 bis provided to be connected to an external terminal such as an FPC 1823.Besides, reference numeral 1819 designates a liquid crystal material;and 1820, an opposite electrode. Besides, reference numeral 1801designates a first substrate; 1808, a sealing region; and 1821, a secondsubstrate. Reference numeral 1822 denotes an adhesive.

Besides, in this embodiment, columnar spacers 1807 are provided betweena pixel portion and a source side driver circuit, columnar spacers 1809are provided at an external connection terminal portion, columnarspacers 1810 are provided at the pixel portion, columnar spacers 1811are provided at a gate side driver circuit, and columnar spacers 1812are provided at the sealing region. The respective columnar spacers areprovided at a constant interval by a photolithography method. Like this,by providing the columnar spacers at a constant interval, a uniformsubstrate interval can be maintained. Besides, by providing the columnarspacers 1812 at the sealing region, a filler may not be used. Besides,by providing the columnar spacers 1809 at the external connectionterminal portion, the mechanical strength at the connection portion canbe reinforced. Incidentally, the foregoing respective columnar spacersmay be formed by the fabricating method shown in the embodiment 1 or theembodiment 3.

Incidentally, a fabricating process for obtaining the above TFTstructure may use a well-known technique, and is not particularlylimited.

Incidentally, this embodiment can be freely combined with theembodiments 1 to 4.

Embodiment 7

In this embodiment, a case where a columnar spacer of the presentinvention is applied to a liquid crystal display device equipped with atouch panel, will be described with reference to FIG. 22A and FIG. 22B.

FIG. 22A is an external appearance view and a sectional view of aportable information terminal device equipped with an optical touchpanel 3002.

In FIG. 22A, reference numeral 3001 designates a digital camera; 3002, atouch panel; 3003, a liquid crystal panel; 3004, an LED backlight; 3100,a light emitting element; and 3200, a light receiving element.

In the display device equipped with this touch panel, when a fingertipor a pen tip touches the surface of the touch panel 3002, part of alight path “a” from the light emitting element 3100 provided at the endportion of the panel is interrupted, and part of light advances to alight path “b”. Since the light receiving element 3200 corresponding tothe light emitting element having the light path “a”, the part of whichis interrupted does not receive light, it is possible to detect atemporal positional change of a touched place.

In this embodiment, columnar spacers 3005 of the present invention wereused for the liquid crystal panel 3003. The columnar spacers are formedby the fabricating method described in the embodiment 1 or theembodiment 3. By doing so, the mechanical strength is reinforced, and astrong panel can be made. Besides, by means of the columnar spacers ofthe present invention, the substrate interval is hardly changed bypressure from the outside (from the fingertip or pen tip), so that adisplay image is not easily disturbed.

Incidentally, in this embodiment, a transmission type LCD panel usingthe LED backlight is used. However, a reflection type LCD panel using nobacklight may be used. Besides, an LCD panel which can be freely changedto the reflection type or transmission type in accordance with theamount of outer light may be used.

FIG. 22B is an outer appearance view and a sectional view of a portableinformation terminal device equipped with a pen input type touch panel3102.

In FIG. 22B, reference numeral 3102 designates a touch panel; 3103, aliquid crystal panel; 3104, a backlight; and 3105, an input pen.

In the display device equipped with this touch panel, a pressuresensitive type or capacitive type detecting element is provided on thesurface of the touch panel 3102. When the input pen 3105 touches it, atemporal positional change can be detected by the detecting element.

In this embodiment, columnar spacers 3106 of the present invention wereused for the liquid crystal panel 3103. The columnar spacers are formedby the fabricating method described in the embodiment 1 or theembodiment 3. By doing so, the mechanical strength is reinforced, and astrong panel can be made. Besides, by means of the columnar spacers ofthe present invention, the substrate interval is hardly changed bypressure from the outside (from the fingertip or pen tip), so that adisplay image is not easily disturbed. Since the touch panel 3102 inwhich the pressure sensitive type or capacitive type detecting elementis provided is in direct contact with the LCD panel 3103, the LCD panel3103 easily receives pressure from the outside and it is effective.

Incidentally, the structure of this embodiment can be freely combinedwith any structure of the embodiments 1 to 6.

Embodiment 8

A case of applying the present invention to a reflection type liquidcrystal display device formed over a silicon substrate is described. TFTstructure may be realized by adding impurity elements imparting n-typeor p-type directly to the silicon substrate (silicon wafer) instead ofthe active layers comprising the crystalline silicon film inEmbodiment 1. Further, because a reflection type is formed, a metallicfilm having a high reflectance (for example aluminum, silver or an alloyof these (Al—Ag alloy) and so forth may be used as the pixel electrode.

Note that it is possible to freely combine the constitutions of thepresent embodiment with any of Embodiments 1 to 7.

Embodiment 9

The present invention can also be applied to the case in which aninterlayer insulating film is formed over a conventional MOSFET and aTFT is formed thereon. That is, it is also possible to realize athree-dimensionally structured semiconductor device. Further it ispossible to use an SOI substrate such as a SIMOX, Smart-Cut (registeredtrademark by SOITEC INC.), ELTRAN (registered trademark by CANON INC.),etc.

It is possible to freely combine the constitutions of the presentembodiment with any of the structures of Embodiments 1 to 8.

Embodiment 10

It is possible to apply the present invention to an active matrix EL(electro luminescence) display device. An example is shown in FIG. 23.

FIG. 23 is a circuit diagram of the active matrix EL display device.Reference numeral 11 denotes a pixel section; and X-direction drivercircuit 12 and Y-direction driver circuit 13 are provided in itsperipheral. Each pixel of the display section 11 comprises a switchingTFT 14, a storage capacitor 15, a current control TFT 16, an organic ELelement 17. X-direction signal line 18 a (or 18 b) and a Y-directionsignal line 19 a (or 19 b or 19 c) are connected to the switching TFT14. Power supply lines 20 a and 20 b are connected to the currentcontrol TFT 16.

In the active matrix EL display device of the present embodiment, TFTsused for the X-direction driver circuit 12 and the Y-direction drivercircuit 13 are formed by combining a p-channel TFT 701 and an n-channelTFTs 702 or 703 of FIG. 8B. The switching TFT 14 and the current controlTFT 16 are formed from an n-channel TFT 704 of FIG. 8B.

Embodiment 11

It is possible to use a variety of liquid crystal materials in a liquidcrystal display device manufactured in accordance with the presentinvention. The following can be given as examples of the such materials:a TN liquid crystal; a PDLC (polymer diffusion type liquid crystal); anFLC (ferroelectric liquid crystal); an AFLC (antiferroelectric liquidcrystal); and a mixture of an FLC and an AFLC.

For example, the liquid crystal materials disclosed in: Furue, H, etal., “Characteristics and Driving Scheme of Polymer-stabilizedMonostable FLCD Exhibiting Fast Response Time and High Contrast Ratiowith Gray-scale Capability,” SID, 1998; in Yoshida, T., et al., “AFull-color Thresholdless Antiferroelectric LCD Exhibiting Wide ViewingAngle with Fast Response Time,” SID 97 Digest, 841, 1997; and in U.S.Pat. No. 5,594,569 can be used.

In particular, when an antiferroelectric liquid crystal having nothreshold (thresholdless) (thresholdless antiferroelectric LCD:abbreviated to TL-AFLC) is used, in some cases the power supply voltageof 5 to 8 is sufficient because the operating voltage of liquid crystalis reduced to approximately ±2.5V. Namely, it becomes possible to drivethe driver circuits and the pixel matrix circuits at the same powersupply voltage, so that the electric power consumption of the liquidcrystal display device as a whole can be reduced.

Further, there are some that exhibit electro-optical responsecharacteristics of V shape among thresholdless antiferroelectric LCD andthose having the driver voltage of approximately ±2.5 V (cell thicknessapproximately 1 to 2 mm) is even found.

The characteristic of light transmittivity against applied voltage, of athresholdless antiferroelectric mixed liquid crystal which shows aV-shaped electro-optical response is shown here in FIG. 24. The verticalaxis of the graph shown in FIG. 24 is the transmissivity (in arbitraryunits), and the horizontal axis is the applied voltage. Note that thetransmission axis of the polarizing plate on the incidence side is setnearly in agreement with the rubbing direction of the liquid crystaldisplay device, and nearly parallel to the direction normal to thesmectic layer of the thresholdless antiferroelectric mixed liquidcrystal. Further, the transmission axis of the polarizing plate on theoutgoing side is set nearly perpendicular (crossed Nicols) to thetransmission axis of the polarizing plate on the incidence side.

Further, ferroelectric liquid crystals and anti-ferroelectric liquidcrystals possess an advantage in that they have a high response speedcompared to TN liquid crystals. Since it is possible to realize anextremely fast operating speed TFT used in the present invention, it ispossible to realize a liquid crystal display device with fast imageresponse speed by sufficiently utilizing the fast response speed offerroelectric liquid crystals and antiferroelectric liquid crystals.

It is needless to say that the use of the liquid crystal display deviceof the present embodiment to a display for an electronic device such asa personal computers, etc., is effective.

It is possible to freely combine the constitutions of the presentembodiment with any constitutions of Embodiments 1 to 10.

Embodiment 12

The TFTs formed by implementing the present invention can be used invarious electro-optical devices. Namely the present invention can beimplemented on all of the electronic appliances that incorporate theseelectro-optical devices as a display.

The following can be given as examples of this type of electronicappliances: video cameras; digital cameras; head mounted displays(goggle type displays); wearable displays; car navigation systems;personal computers; portable information terminals (such as mobilecomputers, portable telephones and electronic notebooks). Some examplesof these are shown in FIGS. 25A to 25F.

FIG. 25A is a personal computer, which comprises: a main body 2001; animage input section 2002; a display section 2003; and a keyboard 2004.The present invention can be applied to the image input section 2002,display section 2003 and other driver circuits.

FIG. 25B is a video camera, which comprises: a main body 2101; a displaysection 2102; a voice input section 2103; operation switches 2104; abattery 2105; and an image receiving section 2106. The present inventioncan be applied to the display section 2102, the voice input section 2103or other driver circuits.

FIG. 25C is a mobile computer which comprises: a main body 2201; acamera section 2202; an image receiving section 2203; operation switches2204; and a display section 2205. The present invention can be appliedto the display section 2205 or other driver circuits.

FIG. 25D is a goggle type display which comprises: a main body 2301; adisplay section 2302; and an arm section 2303. The present invention canbe used for the display section 2302 or other driver circuits.

FIG. 25E is a player that uses a recording medium on which a program isrecorded (hereinafter referred to as a recording medium), whichcomprises: a main body 2401; a display section 2402; a speaker section2403; a recording medium 2404; and operation switches 2405 etc. Notethat music appreciation, film appreciation, games, and the use of theInternet can be performed with this device using a DVD (digitalversatile disk), a CD, etc., as a recording medium. The presentinvention can be applied to the display sections 2402 or other drivercircuits.

FIG. 25F is a digital camera which comprises: a main body 2501; adisplay section 2502; a view finder section 2503; operation switches2504; and an image receiving section (not shown in the figure). Thepresent invention can be applied to the display section 2502 or otherdriver circuits.

As described above, the applicable range of the active matrix displaydevice of the present invention is very large, and it is possible toapply to electronic appliances of various areas. Further, the electricappliances of the present embodiment can be realized by any combinationof constitutions of Embodiments 1 to 9 and 11.

Embodiment 13

The TFTs formed by implementing the present invention can be used invarious electro-optical devices. Namely the present invention can beimplemented on all of the electronic appliances that incorporate theseelectro-optical devices as a display.

Projectors (rear type or front type) can be given as such electronicappliances. The examples are shown in FIGS. 26A to 26D.

FIG. 26A is a front projector which comprises a display section 2601 anda screen 2602. The present invention can be applied to the displaysection 2601 or other driver circuits.

FIG. 26B is a rear projector which comprises: a main body 2701, adisplay section 2702, a mirror 2703 and a screen 2407. The presentinvention can be applied to the display section 2702 or other drivercircuits.

Note that FIG. 26C is a diagram showing an example of the structure ofthe display sections 2601 and 2702 in FIGS. 26A and 26B. The displaysections 2601 and 2702 comprise: an optical light source system 2801;mirrors 2802 and 2804 to 2806; a dichroic mirror 2803; a prism 2807; aliquid crystal display device 2808; a phase differentiating plate 2809;and a projection optical system 2810. The projection optical system 2810comprises an optical system including projection lens. Though thepresent embodiment shows an example of 3-plate type, it is not limitedto the 3-plate type, for example, single plate type is appropriate.Further, an operator may properly dispose an optical lens, a film havinglight polarizing function, a film adjusting phase difference, IR filmsand so forth in the optical path shown by an arrow in FIG. 26C.

FIG. 26D is a diagram showing an example of the structure of the opticallight source system 2801 in FIG. 26C. In the present embodiment theoptical light source system 2801 comprises: a reflector 2811; a lightsource 2812; lens arrays 2813 and 2814; light polarizing conversionelement 2815; and a condenser lens 2816. Note that the optical lightsource system shown in FIG. 26D is merely an example and the structureis not specifically limited. For example, an operator may properlydispose an optical lens, a film having light polarizing function, a filmadjusting phase difference, IR films and so forth in the optical lightsource system. As described above, the applicable range of the presentinvention is very large, and it is possible to apply to electronicappliances of various areas. Further, the electric appliances of thepresent embodiment can be realized by any combination of theconstitutions of Embodiments 1 to 9 and 11.

By using the columnar spacer of the present invention, it is possible toprovide, without using a particulate spacer, a high quality liquidcrystal panel having a thickness with high accuracy, which is designedwithin a free range in accordance with characteristics of a used liquidcrystal and a driving method.

Besides, by adopting, the shape of the columnar spacer of the presentinvention, defective orientation in liquid crystal can be prevented.

Besides, by using the columnar spacer of the present invention, a loadapplied to an element is reduced, and it becomes possible to prevent thelowering of yield due to element destruction or the like and lowering ofreliability. Like this, it is possible to achieve the improvement ofoperation performance and improvement of reliability of anelectro-optical device typified by a liquid crystal display device.

1. (canceled)
 2. A display device comprising: a first substrate; a firstsemiconductor layer over the first substrate, the first semiconductorlayer comprising a channel formation region; a first pixel electrodeelectrically connected to the first semiconductor layer; a secondsemiconductor layer over the first substrate, the second semiconductorlayer comprising a channel formation region; a second pixel electrodeelectrically connected to the second semiconductor layer; a secondsubstrate over the first pixel electrode and the second pixel electrode;and a photolithographic spacer between the first substrate and thesecond substrate, wherein the photolithographic spacer overlaps with thefirst semiconductor layer, and wherein no photolithographic spaceroverlaps with the second semiconductor layer.
 3. The display deviceaccording to claim 2, further comprising: a gate electrode under thefirst semiconductor layer; an insulating layer between the gateelectrode and the first semiconductor layer; a wiring over andelectrically connected to the first semiconductor layer; and aninterlayer insulating layer over the wiring, wherein thephotolithographic spacer overlaps with the gate electrode, theinsulating layer, the wiring, and the interlayer insulating layer. 4.The display device according to claim 2, wherein the photolithographicspacer has a cross-section in which a value obtained by dividing a widthof a second substrate side end portion of the photolithographic spacerby a width of a center portion of the photolithographic spacer is largerthan or equal to 0.8 and smaller than or equal to
 3. 5. The displaydevice according to claim 2, further comprising: a third semiconductorlayer over the first substrate, the third semiconductor layer comprisinga channel formation region; and a third pixel electrode electricallyconnected to the third semiconductor layer, wherein no photolithographicspacer overlaps with the third semiconductor layer, and wherein thethird pixel electrode is adjacent to the first pixel electrode and thesecond pixel electrode.
 6. The display device according to claim 2,wherein a sectional shape of the photolithographic spacer is aquadrilateral or a polygon having sides more than four.
 7. The displaydevice according to claim 2, further comprising: a liquid crystal layerover the first pixel electrode and the second pixel electrode.
 8. Thedisplay device according to claim 2, wherein the channel formationregion of each of the first semiconductor layer and the secondsemiconductor layer comprises silicon.
 9. A display device comprising: afirst substrate; a first semiconductor layer over the first substrate,the first semiconductor layer comprising a channel formation region; afirst pixel electrode electrically connected to the first semiconductorlayer; a second semiconductor layer over the first substrate, the secondsemiconductor layer comprising a channel formation region; a secondpixel electrode electrically connected to the second semiconductorlayer; a second substrate over the first pixel electrode and the secondpixel electrode; and a plurality of photolithographic spacers betweenthe first substrate and the second substrate, wherein aphotolithographic spacer of the plurality of photolithographic spacersoverlaps with the first semiconductor layer, wherein nophotolithographic spacer overlaps with the second semiconductor layer,and wherein the plurality of photolithographic spacers are disposed at adensity of 10 to 200/mm².
 10. The display device according to claim 9,further comprising: a gate electrode under the first semiconductorlayer; an insulating layer between the gate electrode and the firstsemiconductor layer; a wiring over and electrically connected to thefirst semiconductor layer; and an interlayer insulating layer over thewiring, wherein the photolithographic spacer overlaps with the gateelectrode, the insulating layer, the wiring, and the interlayerinsulating layer.
 11. The display device according to claim 9, whereinthe photolithographic spacer has a cross-section in which a valueobtained by dividing a width of a second substrate side end portion ofthe photolithographic spacer by a width of a center portion of thephotolithographic spacer is larger than or equal to 0.8 and smaller thanor equal to
 3. 12. The display device according to claim 9, furthercomprising: a third semiconductor layer over the first substrate, thethird semiconductor layer comprising a channel formation region; and athird pixel electrode electrically connected to the third semiconductorlayer, wherein no photolithographic spacer overlaps with the thirdsemiconductor layer, and wherein the third pixel electrode is adjacentto the first pixel electrode and the second pixel electrode.
 13. Thedisplay device according to claim 9, wherein a sectional shape of thephotolithographic spacer is a quadrilateral or a polygon having sidesmore than four.
 14. The display device according to claim 9, whereineach of the plurality of photolithographic spacers is disposed for everysix pixels.
 15. The display device according to claim 9, furthercomprising: a liquid crystal layer over the first pixel electrode andthe second pixel electrode.
 16. The display device according to claim 9,wherein the channel formation region of each of the first semiconductorlayer and the second semiconductor layer comprises silicon.
 17. Adisplay device comprising: a first substrate; a first semiconductorlayer over the first substrate, the first semiconductor layer comprisinga channel formation region; a first pixel electrode electricallyconnected to the first semiconductor layer; a second semiconductor layerover the first substrate, the second semiconductor layer comprising achannel formation region; a second pixel electrode electricallyconnected to the second semiconductor layer; a third semiconductor layerover the first substrate, the third semiconductor layer comprising achannel formation region; a third pixel electrode electrically connectedto the third semiconductor layer; a second substrate over the firstpixel electrode, the second pixel electrode and the third pixelelectrode; a photolithographic spacer between the first substrate andthe second substrate; a liquid crystal layer over the first pixelelectrode, the second pixel electrode and the third pixel electrode; agate electrode under the first semiconductor layer; an insulating layerbetween the gate electrode and the first semiconductor layer; a wiringover and electrically connected to the first semiconductor layer; aninterlayer insulating layer over the wiring, wherein thephotolithographic spacer overlaps with the gate electrode, theinsulating layer, the wiring, and the interlayer insulating layer,wherein the photolithographic spacer overlaps with the firstsemiconductor layer, wherein no photolithographic spacer overlaps withthe second semiconductor layer, wherein no photolithographic spaceroverlaps with the third semiconductor layer, wherein the third pixelelectrode is adjacent to the first pixel electrode and the second pixelelectrode, and wherein the photolithographic spacer has a cross-sectionin which a value obtained by dividing a width of a second substrate sideend portion of the photolithographic spacer by a width of a centerportion of the photolithographic spacer is larger than or equal to 0.8and smaller than or equal to 3, and a width of a first substrate sideend portion of the photolithographic spacer by the width of the centerportion of the photolithographic spacer is larger than or equal to 1 andsmaller than or equal to 2.5.
 18. The display device according to claim17, wherein a sectional shape of the photolithographic spacer is aquadrilateral or a polygon having sides more than four.
 19. The displaydevice according to claim 17, wherein the channel formation region ofeach of the first semiconductor layer, the second semiconductor layerand the third semiconductor layer comprises silicon.